Stacked semiconductor chips in a single semiconductor package
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United States of America Patent
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Jan 15, 2002
Issued Date -
N/A
app pub date -
Oct 22, 1999
filing date -
Oct 24, 1998
priority date (Note) -
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Abstract
A stacked semiconductor chip package includes: a substrate including a plurality of conductive pads; a first semiconductor chip mounted on the substrate; and electrically connected to the conductive pads; a plurality of electrical leads provided about the substrate; a first molding part for sealing the substrate and the first semiconductor chip; a second semiconductor chip mounted on an upper surface of the first molding part and electrically connected to the electrical leads; and a second molding part for sealing the second semiconductor chip, the second conductive wires and a portion of the leads.
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