Data I/O buffer control circuit
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United States of America Patent
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Jan 15, 2002
Grant Date -
N/A
app pub date -
Sep 28, 1999
filing date -
Nov 24, 1998
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).
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