Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
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United States of America Patent
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Jan 22, 2002
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N/A
app pub date -
Jan 11, 2000
filing date -
Mar 22, 1995
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Abstract
A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
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