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Abstract

A semiconductor memory circuit comprises a sense amplifier, a first data storing circuit for temporally storing and outputting the data from the sense amplifier in response to a latch signal and erasing the stored data in response to a first clear signal, a first determination circuit for determining whether the first data storing circuit stores the data and outputting a first determination signal representing the determination. The semiconductor memory circuit further comprises an output data bus, a first transfer circuit transferring the data output from the first data storing circuit to the output data bus in response to the first determination signal, a first clear signal generation circuit for generating the first clear signal in response to the first determination signal, a second data storing circuit for temporally storing and outputting the data output from the first data storing circuit in response to the latch signal and erasing the stored data in response to a second clear signal, a second determination circuit for determining whether the second data storing circuit stores the data and outputting a second determination signal representing the determination, a second transfer circuit for transferring the data output from the second data storing circuit to the data bus in response to the second determination signal and a second clear signal generation circuit for generating the second clear signal in response to the second determination signal.

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First Claim