Apparatus and process for pattern distortion detection for semiconductor process and semiconductor device manufactured by use of the apparatus or process
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 29, 2002
Grant Date -
N/A
app pub date -
Dec 2, 1998
filing date -
Dec 5, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A finished pattern that will be formed based on a design layout pattern in a semiconductor manufacturing process is predicted, and the outline of the predicted finished pattern is converted into a polygon. On the other hand, test reference patterns are formed based on the design layout pattern. A pattern distortion in the predicted finished pattern is detected by comparing the polygonized predicted finished pattern with the test referencepatterns. In converting the predicted finished pattern into a polygon, the number of apices of the polygon is reduced. Two kinds of test reference patterns are formed: an upper limit test reference pattern obtained by reducing the design layout pattern and defining an allowable upper limit and a lower limit test reference pattern obtained by enlarging the design layout pattern and defining an allowable lower limit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully