US Patent No: 6,344,371
Number of patents in Portfolio can not be more than 2000
Dimensionally stable core for use in high density chip packages and a method of fabricating same
Stats
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Feb 5, 2002
Issued date -
Aug 19, 1998
filing date -
09/136,201
serial no -
In Force
status
Importance
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Abstract
A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 4,868,350 High performance circuit boards | 29 | 1988 | |
| 4,854,038 Modularized fabrication of high performance printed circuit boards | 37 | 1988 | |
| 5,129,142 Encapsulated circuitized power core alignment and lamination | 83 | 1990 | |
| 5,103,293 Electronic circuit packages with tear resistant organic cores | 56 | 1990 | |
| 5,224,265 Fabrication of discrete thin film wiring structures | 92 | 1991 | |
| 5,232,548 Discrete fabrication of multi-layer thin film, wiring structures | 46 | 1991 | |
| 5,301,118 Monte carlo simulation design methodology | 63 | 1991 | |
| 5,199,163 Metal transfer layers for parallel processing | 23 | 1992 | |
| 5,548,034 Modified dicyanate ester resins having enhanced fracture toughness | 6 | 1992 | |
| 5,523,148 Multilayer article comprising a toughened polycyanurate with embedded electrically conductive patterns | 6 | 1994 | |
| 5,527,593 Structures fabricated from toughened polycyanurate | 4 | 1994 | |
| 5,527,838 Toughened polycyanurate resins containing particulates | 15 | 1994 | |
| 5,529,836 Multilayer article comprising a toughened polycyanurate | 6 | 1994 | |
| 5,599,611 Prepreg and cured laminate fabricated from a toughened polycyanurate | 18 | 1994 | |
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| 4,482,516 Process for producing a high strength porous polytetrafluoroethylene product having a coarse microstructure | 201 | 1982 | |
| 4,680,220 Dielectric materials | 67 | 1985 | |
| 4,985,296 Polytetrafluoroethylene film | 178 | 1989 | |
| 5,383,788 Electrical interconnect assembly | 39 | 1993 | |
| 5,498,467 Process for preparing selectively conductive materials by electroless metal deposition and product made therefrom | 38 | 1994 | |
| 5,753,358 Adhisive-filler polymer film composite | 23 | 1996 | |
| 5,841,075 Method for reducing via inductance in an electronic assembly and article | 39 | 1998 | |
| 5,919,329 Method for assembling an integrated circuit chip package having at least one semiconductor device | 43 | 1998 | |
| 5,970,319 Method for assembling an integrated circuit chip package having at least one semiconductor device | 19 | 1999 | |
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| 5,034,801 Intergrated circuit element having a planar, solvent-free dielectric layer | 56 | 1989 | |
| 5,731,047 Multiple frequency processing to improve electrical resistivity of blind micro-vias | 31 | 1996 | |
| 5,863,446 Electrical means for extracting layer to layer registration | 11 | 1996 | |
| 5,868,950 Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques | 12 | 1996 | |
| 5,879,787 Method and apparatus for improving wireability in chip modules | 55 | 1996 | |
| 5,910,255 Method of sequential laser processing to efficiently manufacture modules requiring large volumetric density material removal for micro-via formation | 20 | 1996 | |
| 5,965,043 Method for using ultrasonic treatment in combination with UV-lasers to enable plating of high aspect ratio micro-vias | 19 | 1996 | |
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| 5,509,200 Method of making laminar stackable circuit board structure | 55 | 1994 | |
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| 4,997,698 Ceramic coated metal substrates for electronic applications | 34 | 1989 | |
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| 5,436,062 Process for the production of printed circuit boards with extremely dense wiring using a metal-clad laminate | 39 | 1994 | |
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| 5,652,284 Thermoplastic elastomer-asphalt nanocomposite composition | 9 | 1995 | |
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| 5,638,598 Process for producing a printed wiring board | 16 | 1995 | |
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| 4,642,160 Multilayer circuit board manufacturing | 184 | 1985 | |
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| 5,639,808 Flame retardant thermosettable resin compositions | 13 | 1996 | |
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| 4,894,271 Metal-core printed wiring board and a process for manufacture thereof | 16 | 1988 | |
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| 5,512,390 Light-weight electrical-storage battery | 10 | 1994 | |
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| 5,045,642 Printed wiring boards with superposed copper foils cores | 21 | 1990 | |
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| 4,705,762 Process for producing ultra-fine ceramic particles | 82 | 1985 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Aug 5, 2013 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |