System and method for testing high speed VLSI devices using slower testers
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United States of America Patent
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Feb 5, 2002
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N/A
app pub date -
Apr 22, 1999
filing date -
Mar 29, 1999
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Abstract
At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.
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