Verification of message sequence charts
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Feb 12, 2002
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N/A
app pub date -
May 5, 2000
filing date -
May 5, 2000
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Abstract
A method for checking a property of a system modeled with a hierarchical message sequence chart is provided. To check a property of the modeled system, a temporal logic causality specification is defined. The specification is translated to a specification automaton, and an implementation automaton is constructed from the hierarchical message sequence chart. The intersection of the automata are then checked for emptiness.
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