System for optimizing the testing and repair time of a defective integrated circuit
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United States of America Patent
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Feb 12, 2002
Issued Date -
N/A
app pub date -
Jul 7, 2000
filing date -
Aug 7, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
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