Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
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United States of America Patent
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Feb 19, 2002
Grant Date -
N/A
app pub date -
Mar 12, 1999
filing date -
Mar 12, 1999
priority date (Note) -
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Abstract
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.
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