Programmable logic device with unified cell structure including signal interface bumps
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Feb 26, 2002
Grant Date -
N/A
app pub date -
Jul 13, 2000
filing date -
Jul 15, 1999
priority date (Note) -
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Abstract
A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball.
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