Built-in self-test circuit and method for validating an associative data array
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United States of America Patent
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Feb 26, 2002
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N/A
app pub date -
May 29, 1998
filing date -
May 29, 1998
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Abstract
There is disclosed, for use in a processing device having an N-way set associative data array (such as an L1 cache), a built-in self-test (BIST) circuit for testing the validity of storage locations in the data array. The BIST circuit comprises 1) a memory capable of storing a test program executable by the processing device, wherein the test program is capable of testing the validity of the storage locations in the data array; and 2) a controller capable of copying the test program from the memory into first selected storage locations in a first way in the data array, wherein the processing device executes the copied test program stored in the first selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.
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