Staged aluminum deposition process for filling vias

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United States of America Patent

PATENT NO 6352620
APP PUB NO 20010047932A1
SERIAL NO

09340977

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Abstract

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The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abburi, Murali Santa Clara, CA 10 141
Cha, Yonghwa Chris San Jose, CA 12 1280
Chen, Fufa Cupertino, CA 30 893
Singhvi, Shri Milpitas, CA 4 90
Yu, Sang-Ho Sunnyvale, CA 33 1968

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