Method of depositing amorphous silicon based films having controlled conductivity

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United States of America Patent

PATENT NO 6352910
SERIAL NO

09249041

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Abstract

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Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.

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Patent Owner(s)

Patent OwnerAddress
APPLIED KOMATSU TECHNOLOGY INCP O BOX 450-A SANTA CLARA CA 95052

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feng, Guofu J San Jose, CA 5 122
Harshbarger, William R San Jose, CA 33 1848
Law, Kam Union City, CA 18 601
LeGrice, Yvonne Walnut, CA 4 30
Olsen, Jeff C Los Gatos, CA 3 39
Qiu, Regina Cupertino, CA 4 30
Robertson, Robert M Santa Clara, CA 5 147
Takehara, Takako Hayward, CA 28 405

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