Method and apparatus for reducing interconnect resistance using an interconnect well
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United States of America Patent
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Mar 5, 2002
Grant Date -
N/A
app pub date -
May 3, 1999
filing date -
May 3, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.
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