Importance

Loading Importance Indicators...

Abstract

An apparatus embodiment of the present invention includes a memory array with lines of memory cells. The lines are coupled to respective wordlines. The lines may be selected by a wordline signal that is asserted responsive to a first clock signal being asserted. The apparatus also includes 'write wordline' generators coupled to respective ones of the wordlines. A write wordline generator will assert a write wordline signal responsive to a second clock signal being asserted and before the next time the first clock signal is asserted, but after the first clock signal is deasserted. The apparatus further includes a comparator, which has a first set of inputs coupled to bit lines of the memory cells for reading the contents of the cells, and a second set of inputs for reading a data value. The comparator has a compare match output upon which it asserts a compare match signal if the contents matches the data value. In response to the compare match and write wordline signals, a write operation occurs for the line. Due to the timing of the write wordline signal, the write operation advantageously occurs in the same clock cycle during which the line was selected without any additional decoding.

Loading the Abstract Image...

First Claim