Reconfigurable processor devices
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United States of America Patent
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Mar 5, 2002
Grant Date -
N/A
app pub date -
Dec 11, 1998
filing date -
Dec 17, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the processing devices comprises an arithmetic logic unit, which is adapted to perform a function on input operands and produce an output. The input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle. Dynamic instructions are enabled by means provided to route the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.
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