Multifunction memory array in a programmable logic device
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United States of America Patent
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Mar 12, 2002
Grant Date -
N/A
app pub date -
Sep 29, 2000
filing date -
Apr 3, 2000
priority date (Note) -
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Abstract
A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).
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