Method for halftoning using interlocked threshold arrays or interlocked dot profiles
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United States of America Patent
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Mar 12, 2002
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app pub date -
Jan 31, 2000
filing date -
Sep 30, 1997
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Abstract
A dispersed-dot stochastic dither array is provided for rendering halftone images having excellent visual quality. For color printing, a separate threshold array is generated for each of the color planes, however, the stochastic screens are interlocked so that the threshold arrays are generated while considering the other color threshold arrays. In this manner, a blue noise distribution may be produced by the individual arrays as well as by any combination of the individual arrays. When generating a single threshold array for a color plane, a particular criterion is used to determine where the next threshold value should be located, and the selection of a threshold location in each array considers the criterion for all the threshold arrays being generated. By using the interlocked threshold arrays approach, the overall visual affect will be improved for both individual threshold arrays and for a combination of more than one of the threshold arrays. The present invention also is used to generating a set of interlocked dot profiles which do not use a threshold array for halftoning. In an opposite sense, the interlocked threshold arrays can be generated without using dot profiles during the formative steps of the threshold array. More than one threshold array could be generated in this manner, and these threshold arrays could also be interlocked with respect to one another. Other alternative methodologies include globally optimizing interlocked threshold arrays by simultaneously considering all tone levels for all threshold arrays being generated to avoid locally suboptimal solutions; or regional optimization can be achieved to simultaneously considering certain portions of the tone levels. Also, interlocked threshold arrays can be created that obtain better data compression, or to embed a digital watermark.
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Patent Owner(s)
- FUNAI ELECTRIC CO., LTD.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Cooper, Brian Edward | Lexington, KY | 10 | 198 |
Love, Shaun Timothy | Lexington, KY | 14 | 249 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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