Reduced power DRAM device and method
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United States of America Patent
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Mar 12, 2002
Grant Date -
N/A
app pub date -
Aug 23, 2000
filing date -
Aug 23, 2000
priority date (Note) -
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Abstract
A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
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