Pooled receive and transmit queues to access a shared bus in a multi-port switch asic
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United States of America Patent
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Mar 12, 2002
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N/A
app pub date -
Jun 29, 1998
filing date -
Jun 29, 1998
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Abstract
A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.
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