Importance

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Abstract

A modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. Output and input circuitry is provided in conjunction with the polling master and user ATM boards to accommodate hot insertion and to help drive the circuit. The master preferably includes an outgoing address latch and address latch control associated with the address bus, and a register associated with the enable signal. The master also includes a hot insertion buffer on the incoming cell available signal. The user device(s) include hot insertion buffers on the address bus, the data bus, and the enable signal. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot-insertable UTOPIA interface is established.

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First Claim