Dual aspect ratio PE array with no connection switching
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United States of America Patent
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Mar 12, 2002
Grant Date -
N/A
app pub date -
Oct 25, 2000
filing date -
Oct 26, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A single-instruction multiple-data (SIMD) array processor for processing multi-dimensional node meshes that are either elongated or not elongated in at least one coordinate direction. The SIMD array processor includes a plurality of processor arrays interconnected to form an N-dimensional array. Each processor array in the N-dimensional array is connected to 2N data I/O paths for communicating with 2N processor arrays in the N-dimensional array. Each processor array conceptually located at an interior point of the N-dimensional array is connected to 2N dimensionally adjacent processor arrays in the N-dimensional array. Each processor array conceptually located at one of at least one pair of dimensionally opposite boundaries of the N-dimensional array is connected to fewer than 2N dimensionally adjacent processor arrays and at least one processor array conceptually located at the dimensionally opposing boundary.
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