Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
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United States of America Patent
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Mar 19, 2002
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app pub date -
Jul 28, 1998
filing date -
Jul 28, 1998
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Abstract
The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.
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