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Abstract

A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure. In response to detecting the failure of the first clock source, the switching logic is configured to cause the input clock signal from a second clock source to be provided to the phase detector. This configuration may advantageously maintain lock in the PLL circuit while switching between clock sources for the input clock signal. The phase detector may further include a pulse width limiting circuit. The pulse width limiting circuit is configured to shorten each phase error output signal by a predetermined amount.

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First Claim