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Abstract

A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a 'read' or a 'write') and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and a state machine to generate command signals from the latched command bits.

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