Microelectronic unit forming methods and materials
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United States of America Patent
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Mar 26, 2002
Grant Date -
N/A
app pub date -
May 24, 1999
filing date -
Jul 7, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
Electrically conductive elements such as terminals and leads are held on a support structure by a degradable connecting layer such as a adhesive degradable by heat or radiant energy. After connecting these elements to a microelectronic element such as a chip or wafer, the conductive elements are released from the support structure by degrading the connecting layer. The support structure desirably has a predictable, isotropic coefficient of thermal expansion and such coefficient of thermal expansion may be close to that of silicon to minimize the effect of the temperature changes. The conductive elements may be mounted on a plurality of individual tiles rather than on an unitary sheet covering an entire wafer to minimize dimensional changes when the dielectric is released from the support structure.
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