Importance

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Abstract

A CDMA reverse link has a system for providing compensation for phase errors caused by clock jitter in a CDMA reverse link. After filtering, data spread by a pilot PN sequence is supplied to a shift register that produces several data samples for sequential cycles of an internal clock. A memory stores compensation factors representing the clock jitter, pre-calculated for each of the internal clock cycles. A counter counts the internal clock cycles to provide the memory with an address signal indicating a memory location that stores the compensation factor for a current internal clock cycle. Based on the data samples and the compensation factor, an interpolator performs an interpolation algorithm to determine an adjusted spread data value that compensates for phase errors caused by jitter in the internal clock.

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First Claim