Adder circuit with the ability to detect zero when rounding
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United States of America Patent
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Apr 2, 2002
Grant Date -
N/A
app pub date -
Mar 31, 1999
filing date -
Mar 31, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
An adder circuit uses a summing circuit to provide a summed sliced bit number from a first sliced bit number and a second sliced bit number. A boundary circuit is operably connected to the summing circuit to form a rounding boundary between selected groups of the summed sliced bit number. A rounding circuit is operably connected to the boundary circuit to detect a zero in each slice of the summed sliced bit number while the first and second sliced bit numbers are being added to one another. The rounding circuit includes a logic circuit to detect the zero and provide a zero detect output and a control circuit to selectively round the summed sliced bit number up and down in response to the zero detect output.
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