Importance

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Abstract

A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an access enable line 12. An index decoder 46 is provided for controlling cache replacement and cache maintenance operations. The hit line 18 is used for passing both hit signals to the cache RAM 28 and select signals generated by the index decoder 46. A gate 36 operating under control of a multiplexer controller 44 controls this dual-use of the hit line 18 in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory 22. A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch 43. Upon a subsequent cycle the latched hit signal can be passed to an access enable line 12 to permit a new TAG value corresponding to a second address B to be written to the content addressable memory 24. The cached data values from the first address A are now present within the cache memory system 22 associated with a TAG value of the second address B. The dirty bit may be set to ensure that writeback occurs when the data value is removed from the cache memory 22 thereby ensuring data integrity.

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First Claim