System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch
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United States of America Patent
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Apr 2, 2002
Issued Date -
N/A
app pub date -
Oct 2, 2000
filing date -
Apr 21, 1998
priority date (Note) -
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Abstract
A computer implemented method in a processor to perform a backing store switch from a first context (source context) to a second context (target context) is provided whereby the backing store memory image and RSE will be synchronized with the processor's execution of instructions. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers. The processor further includes a register stack engine (RSE) to exchange information in one of an instruction execution dependent and independent modes between a storage area and the RS. The processor further includes a FLUSHRS state machine to notify the RSE to store dirty register in the RS to a backing store located in a memory.
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