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Abstract

A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die. The manufacturing test process then continues for the packaged integrated circuits. As with the unsingulated die, the packaged parts are subjected to one or more sets of stress factors, with data being gathered at each stage. Again, test results (e.g., faulty memory locations as determined by the BIST circuitry) are correlated to specific packaged parts via the identification number of the integrated circuit die. The test results of the various stages are next compared to determine if any detected repairable failures are uniform across the various operating conditions. In general, the assumption is made that an integrated circuit IC which exhibits different failure mechanisms at different stages of the testing/manufacturing process is questionable and the part is discarded.

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First Claim