Method of analyzing a circuit having at least one structural loop within a channel connected component
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United States of America Patent
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Apr 2, 2002
Grant Date -
N/A
app pub date -
Sep 10, 1999
filing date -
Sep 10, 1999
priority date (Note) -
Expired
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Abstract
A method of analyzing a circuit having at least one structural loop within a channel connected component first requires that the circuit be at least partly notionally split into its constituent channel connected components (100). The structural loops within a channel-connected component are then detected and a pair of temporary boolean variables is inserted at a break point in each structural loop in the channel-connected component at an internal input. The channel connected component is then analyzed utilizing the pairs of temporary boolean variables at the break points in order to obtain a pair of boolean equations at each break point representing the functionality of the channel connected component at that break point to produce a system of boolean equations for the break points within the channel connected component (101). The system of boolean equations is then solved to produce a result that indicates whether the channel connected component has oscillatory, combinational or sequential behavior.
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