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Abstract

In a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit operates the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal.

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First Claim