High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
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United States of America Patent
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Apr 9, 2002
Grant Date -
N/A
app pub date -
Sep 14, 1999
filing date -
Jul 23, 1999
priority date (Note) -
Expired
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Abstract
The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
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