Method and system for maintaining hierarchy throughout the integrated circuit design process
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United States of America Patent
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Apr 9, 2002
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app pub date -
Jan 20, 2000
filing date -
May 7, 1996
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Abstract
A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automtically selected and applied during implementation of a placement algorithm.
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