Importance

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Abstract

A high performance dynamic memory array architecture is disclosed in several embodiments. The row decoders drive the selected word line to a boosted VPP voltage that is internally generated by a charge pump type circuit whose output is a substantially fixed voltage which is regulated with respect to VSS (i.e., ground). It is substantially independent of VDD over process and environmental variations. The VPP voltage is also used to boost selected array select signals from VDD to VPP. For typical operating voltages, the VPP voltage is somewhat higher than VDD, although at low operating voltage the VPP voltage may be substantially higher than VDD, while at very high operating voltage, the VPP voltage may be similar in magnitude to the VDD voltage. In a preferred embodiment, the VPP generator includes a plurality of pump circuits, each connected to the VPP output, and each controlled by a common control circuit. Each such pump circuit is enabled to pump according to the amount of charge which is needed at a particular time, based on the measured level of both VDD and VPP. If VDD is low, then more of the pump circuits are enabled for a given cycle. As VDD increases, fewer such pump circuits are enabled. Similarly, if VPP is particularly low (such as during power-up), then all the pump circuits are enabled, while if VPP is already high enough, then none of the pump circuits are enabled. In a preferred embodiment, none of the pump circuits are enabled if VPP exceeds 4.0 volts, while all of the pump circuits are enabled if VPP is less than 3.8 volts. Between 3.8 and 4.0 volts, the measured values of both VPP and VDD determine how many and what pumping capacity of pump circuits are enabled.

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First Claim