Importance

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Abstract

According to disclosed embodiments, a semiconductor memory is disclosed that includes a memory array connected to a number of registers by a transfer bus of reduced size. Reduction of transfer bus size can be achieved without a significant increase in data processing speed. According to one embodiment (300) a semiconductor memory can include a number of cell regions (302-0 and 302-1) arranged in a first direction. Sense amplifier banks (304-0 to 304-2) are connected to the cell regions (302-0 and 302-1) and a transfer bus (310-0/1) is disposed over the cell regions (302-0 and 302-1) in the first direction. The transfer bus (310-0/1) includes switching circuits (312-0 and 312-1) corresponding to each cell region (302-0 and 302-1). The switching circuits (312-0 and 312-1) can divide the transfer bus (310-0/1) into a number of transfer bus line portions (314-0/1, 316-0/1 and 318-0/1).

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First Claim