Error checking of simulated printed images with process window effects included
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United States of America Patent
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Apr 16, 2002
Grant Date -
N/A
app pub date -
Jan 25, 1999
filing date -
Jan 25, 1999
priority date (Note) -
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Abstract
A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
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