Fault tolerant computing system using instruction counting
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United States of America Patent
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Apr 16, 2002
Grant Date -
N/A
app pub date -
Jan 19, 1999
filing date -
Jan 20, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In order to provide a microprocessor based fault tolerant computing system, hardware counters or event monitors that are normally included on the microprocessor chips are used to count application instructions that are being executed by the microprocessors. By counting the instructions and preempting the execution of the application program after a predetermined number of instructions have been executed, it is possible to cause the application programs to execute in congruent frames so that results from the application can be checked at congruent points of their execution. If the results do not match, then the program can be terminated or if a number of microprocessors are being used, the results can be voted on and the ones that match can be used in further computation by the system.
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