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Abstract

A method for forming a wide gate stack over a gate in a rf device is described. The invention reduces the gate resistance and the Rs significantly. A substrate has a digital area and a rf area. Devices used in digital circuits will be formed in the digital area and devices used in RF circuits will be formed in the rf area. In both rf and digital areas, gate structure are provided comprising: a gate dielectric and a gate electrode, Source and drain (S/D) regions, source and drain silicide regions, gate silicide regions over the gate electrode. We form a stop layer over the substrate. Next, we form a first interlevel dielectric layer over the stop layer. We polish the first interlevel dielectric layer and the stop layer to expose the gate silicide region. Next, we form a polish stop layer and a second interlevel dielectric layer over the surface. In the digital area, we form a contact holes and in the rf area we to expose the source and drain silicide regions. In the rf area, a wide gate trench top opening is formed through the second interlevel dielectric layer and the polish stop layer to expose gate silicide region. In the digital area, we form contact plugs and in the RF area we form a wide gate top and contact plugs.

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First Claim