Memory system with a non-volatile memory, having address translating function
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United States of America Patent
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Apr 23, 2002
Grant Date -
N/A
app pub date -
Nov 9, 2000
filing date -
Nov 11, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
Logical block addresses are allocated to the blocks provided on a flash memory, respectively. Address translation tables (LTPb's) are provided on the flash memory, each for a group of blocks. Groups of logical block addresses are provided, each group for one group of blocks provided on the flash memory. The logical block addresses of each group have a specific field each. The same data item is contained in the specific fields of the logical block addresses of any group. The data item designates all blocks of the group corresponding to the group of the logical block addresses. Each table has a group of entries storing physical address information indicating the locations that the blocks take in the flash memory. At least one of the tables is stored on a RAM. When a logical address is given from a host system, a microprocessor determines whether a table corresponding to the logical address exists on the RAM. If such table does not exist, the table is copied from the flash memory to the RAM. The microprocessor refers to the corresponding entry in the table on the RAM in accordance with the logical block address contained in the logical address, thereby performing translation from a logical address to a physical address.
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