System and method for invalidating set-associative cache memory with simultaneous set validity determination
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United States of America Patent
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Apr 23, 2002
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N/A
app pub date -
Jul 7, 1997
filing date -
Jul 7, 1997
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Abstract
A system and process for invalidating addresses within a cache memory system is described. The system and process allow a set-associative cache memory system in a computer to simultaneously analyze all sets corresponding to a particular address to determine whether the data at a particular address needs to be written back to the computer's main memory. A set of flags is stored with each address in the cache memory so that the flags can be scrutinized to determine whether the data stored in that set is valid, but not modified.
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