Method of manufacturing thin film transistors
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United States of America Patent
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Apr 30, 2002
Grant Date -
N/A
app pub date -
Mar 27, 2000
filing date -
Mar 27, 1999
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Abstract
A method of manufacturing a top-gate self-aligned thin film transistor involves the use of back exposure of a negative resist (26) using the lower source and drain electrode pattern (11, 12) as a photomask. A transparent amorphous silicon layer (24) is used as the gate electrode layer of the TFT structure, and the resistance of this gate electrode layer (24) is reduced by subsequent processing. For example, a silicide layer (32) may be formed over the gate electrode layer (24) which has the added advantage of reducing the transparency of the insulated gate structure (22, 24) of the TFT, thereby reducing the dependency of the TFT characteristics on light conditions.
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