Testing integrated circuit dice
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 30, 2002
Grant Date -
N/A
app pub date -
Feb 16, 1999
filing date -
Feb 16, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for testing a plurality of integrated circuits. In one embodiment, a plurality of integrated circuits are arranged on a wafer. The integrated circuits are separated on the wafer across the boundary region. Testing interconnects are disposed across the boundary region to test switchable couplings included in each of the integrated circuits on the wafer. After the integrated circuits are tested on the wafer using the testing interconnects across the boundary region, the boundary region is removed, which separates the wafer into individual integrated circuit dice and severs the testing interconnects.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully