Importance

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Abstract

A signal generator (100) receives an input clock signal (X.sub.1) at a first frequency (F.sub.1) and derives an output clock signal (Y) at a second frequency (F.sub.Y). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X.sub.1) and provides a second intermediate signal (X.sub.2) by selectively providing transitions (119) of the second intermediate signal (X.sub.2) at time intervals (T.sub.2 (n)) that are determined by a variable number (A+P(n)) of periods (T.sub.Z) of the first intermediate signal (Z). The second intermediate signal (X.sub.2) has a frequency (F.sub.2) that is in average (F'.sub.2) higher than the first frequency (F.sub.1). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F'.sub.2) and provides the output clock signal (Y).

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First Claim