Semiconductor memory device in which use of cache can be selected
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Apr 30, 2002
Grant Date -
N/A
app pub date -
May 11, 2000
filing date -
May 13, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A semiconductor memory device, includes a plurality of banks, each of which includes a memory cell array and a sense amplifier section, a plurality of channel memories, a data control circuit, a first bus provided between the plurality of banks and the plurality of channel memories, a second bus provided between the plurality of channel memories and the data control circuit, and a third bus between the plurality of banks and the data control circuit. The data control circuit outputs write data to the sense amplifier section of a specified one of the plurality of banks via the third bus in a direct write access mode, and inputs read data from the sense amplifier section of a specified one of the plurality of banks via the third bus in a direct read access mode. Also, the data control circuit outputs write data to the sense amplifier section of a specified one of the plurality of banks via the second bus, a specified one of the plurality of channel memories and the first bus in an indirect write access mode, and inputs read data from the sense amplifier section of a specified one of the plurality of banks via the first bus, a specified one of the plurality of channel memories and the second bus in an indirect read access mode.
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