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Abstract

A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer. In reading data from the FIFO buffer, the read pointer address register is loaded with the previously saved write-pointer address associated with the beginning of each data block that is subsequently read. Since both the beginning and ending write-pointer addresses associated with each data block are captured and saved, the system reading from the FIFO buffer delineates between adjacent data blocks, thereby eliminating data overlap or FIFO interruption.

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