Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation
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United States of America Patent
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Apr 30, 2002
Issued Date -
N/A
app pub date -
Mar 25, 1997
filing date -
Jan 7, 1997
priority date (Note) -
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Abstract
A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.
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