Importance

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Abstract

To provide a semiconductor memory capable of executing a read test at a high speed based on a comparatively complicated test pattern without increasing a circuit area. Every fifth node N1 of a latch L3 of a sense latch group 3 is connected to a gate of an NMOS transistor QLi (i=0 to 3) at 4 intervals and every fifth node N2 is connected to a gate of an NMOS transistor QRi at 4 intervals. The NMOS transistor QLi has a drain connected to a decision result line CHKiL and a source grounded. The NMOS transistor QRi has a drain connected to a decision result line CHKiR and a source grounded. An ALL deciding circuit 5A outputs, as a decision result ALL5, decision result signals ALL0L to ALL3L obtained from decision result lines CHK0L to CHK3L and decision result signals ALL0R to ALL3R obtained from decision result lines CHK0R to CHK3R.

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First Claim